![Verilog Code For Serial Adder Ppt Verilog Code For Serial Adder Ppt](/uploads/1/2/5/6/125676321/404492204.jpg)
What is the Verilog code for a floating point adder/subtractor? Update Cancel. What would the code look like for a Serial Adder in Verilog? Ask New Question. Van-Loi Le, Founder of fpga4student.com. I did an example/ tutorial Verilog code for fixed point multiplication. You can refer to this as an example.
1. Homework Statement
My homework is to design a Serial Adder in Verilog using a shift register module, a full adder module, and a D Flip-Flop module.
I know my full adder and flip flop modules are correct, but I am not so sure about my shift register. The shift register is 8 bits:
Inputs for the shift register are: Si, CLK, Reset
Outputs for the shift register are: So, D7 through D0 (one for each bit of the register)
Also, if anyone can give me a hint as to how I can approach designing a test bench would be extremely helpful.
3. The Attempt at a Solution
My homework is to design a Serial Adder in Verilog using a shift register module, a full adder module, and a D Flip-Flop module.
I know my full adder and flip flop modules are correct, but I am not so sure about my shift register. The shift register is 8 bits:
Inputs for the shift register are: Si, CLK, Reset
Outputs for the shift register are: So, D7 through D0 (one for each bit of the register)
Also, if anyone can give me a hint as to how I can approach designing a test bench would be extremely helpful.
3. The Attempt at a Solution